In modern CMOS designs, as devices have scaled into a regime with channel lengths below 50 nm, the heat generated by the switching of digital logic gates or by their leakage, can no longer be efficiently dissipated through the substrate. Recent developments in silicon technology have exacerbated this issue, while at the same time, interconnect reliability is becoming increasingly subject to electromigration stress in advanced technology nodes due to a breakdown in the classical scaling of such devices. One development has been the use of silicon-on-insulator (SOI) technologies for high-performance CMOS designs. In such technologies, the buried oxide acts as a thermal insulator or barrier between the devices, which dissipate power as they are switched at high frequency, especially when driving heavy loads, and the substrate, acting a heat sink.
Another more recent development has been the introduction of multigate “finFET” technologies, which even when built on a bulk substrate, can result in significant self-heating due to the higher density of active channel width per unit area of silicon, and the high-resistance thermal path to the substrate (either through the fin itself, which is very narrow, or through the field oxide, which has a high thermal resistance). Therefore, self-heating has become a design concern for high-performance circuitry, and is expected to become increasingly important as technology scales to even smaller dimensions.
In the current art, in CMOS digital design methodology frameworks, the circuit temperature is specified as a chip level design parameter, usually matching the modeled substrate temperature for the chip. This is a reasonable assumption for older bulk planar technologies, where the device is fabricated in the bulk silicon itself, with a good thermal connection to the substrate. However it breaks down for SOI technologies, where there is a high-resistance thermal barrier between the device and the substrate. It also breaks down for finFET technologies, where there also is a poor thermal connection to the silicon substrate. In these situations, self-heating can become non-negligible even within regular CMOS logic gates, with high switching factors and/or high output loads. This device-level heating heats up the wires above the hot devices, reducing the electromigration lifetime of the wires, so that any internal logic gate connections, carrying DC current, will suffer a reduced lifetime. Now, in such technologies, thermal modeling techniques have been used to look at specific circuits and specific device heating scenarios. But these thermal modeling techniques require a significant number of computations and calculations for even very simple geometries, as described for example by Shrivastava et al., in IEEE Trans on Electron Devices, vol. 59, page 1353 (2012). No tools or methods currently exist for incorporating the device-self-heating effects, and the impact on electromigration into a digital CMOS design methodology capable of handling designs with hundreds of millions of logic gates. Accordingly, the current state-of-the-art CMOS design methodologies either just ignore any logic-gate self-heating, or apply blanket assumptions to all gates. This can be very pessimistic, if the worst-case temperature increase has to be assumed to apply to all gates, or very optimistic, if the temperature is set at some average value for every gate independent of the actual self-heating that is present.
The basic problem here is that, in conventional design methodologies, the maximum-current limits that are set, based on electromigration statistics for metal lines, do not take into account the device self-heating which would be associated with the generation of that current. Furthermore, it is not easy to do this in a self-consistent way, since the current limit due to electromigration is a complicated, non-linear function of the temperature of the wire. Furthermore, the thermal resistance of a library cell is very difficult to calculate, and can require detailed modeling with a 3D thermal analysis tool, taking into account the details of the structure of the gate, its wiring, the properties of all the different layers and materials making up the devices, and the details of the boundary conditions around the library cell.
It should be noted that Joule self-heating of wires is a well-known phenomenon, and various tools and methodologies have been developed to model the heating, and to guard against it. Furthermore, methods for EM analysis including self-heating treat only self-heating of wires (Joule heating), but not of the devices. Also such methodology is focused on rules designed to avoid any self-heating, not on including those effects in the analysis. The prior art treats self-heating of wires on methods to model, or avoid, wire self-heating, i.e., Joule heating. Other work focuses on self-heating effects on the delay of the gate, and is not applicable to the problem of setting current limits for electromigration robustness.
Referring to FIG. 1, a prior art library characterization flow is shown, covering an aspects of defining the maximum current (limited by electromigration) for each library cell.
Still referring to FIG. 1, starting with 100, a library cell is selected for analysis. Next, in 103, a maximum current, I0 is calculated based on a conventional electromigration analysis of the cell, including as inputs the detailed geometries of the wires, an assumed temperature, and the reliability specifications (electromigration equations, allowed failure rate and the total number of hours of use). The final result is assigned to the cell in question, in 106, and then if there are more library cells to be processed (107) another cell is chosen for analysis. Otherwise, the process terminates (108). In the present analysis, a worst-case temperature can be chosen in 103, in order to guard against the worst-case self-heating that could be encountered in a design application. However, it would be pessimistic to apply it to all cells, since many of the cells would see much less self-heating than the worst-case situation. On another hand, if an “average” temperature is selected, the design can end up with severe reliability exposures since some gates can experience higher temperatures becoming subjected to wear out.